Elliptic curve cryptography (ECC) is one of the most popular public key systems in recent years due to its both high security and low resource consumption. Thus, ECC is more appropriate for Internet applications of Things, which are mainly involved with limited resources. However, non-invasive side channel attacks (SCAs) are considered as a major threat to ECC systems. In this paper, we design a processor for the ECC in the binary field, resistant to differential power attacks (DPA). The main operations in this Architecture are randomized Montgomery multiplication and division units, which make it impossible to create DPAs by involving a random number in the calculation process. The goal is to accelerate the operation by opening the loops in the Montgomery randomized multiplication/division units, and accordingly, Bit-Parallel design instead of Bit serial design. The results show that, despite the complexity of the logic in the two/three-Bit processing versions, the speed is significantly improved by accepting a slight increasing in the area resource. Further, our design is flexible where in the top-level module, depending on the area-speed trade-off, a variety of multiplier and divisor units can be selected. The FPGA evaluations show that in terms of Time×Slice metric, the 2-Bit divider/3-Bit multiplier version of our Architecture leads to 40% improvement over the best previous work. Further, by duplicating the divider and multiplier modules along the Bit-Parallel Architecture this gain can reach to 50%. In terms of operation speed, our design versions are faster than previous work by a factor of 1. 87 and 3. 29. Furthermore, ASIC evaluations in term of Time×Area metric, indicate that deploying 2-Bit multiplier leads to 19% gain relative to previous well-known work. Moreover, duplication of modules along with Bit-Paralleling amplifies the overall gain up to 36%.

In this paper, the structure of a 16-by-16 unsigned hybrid (serial-Parallel) multiplier has been proposed. Parallel multipliers, in comparison with serial multipliers, have higher speed and higher power consumption. In hybrid structures, to reduce power and increase speed, both serial and Parallel techniques are used. The proposed structure improves propagation delay and reduces power consumption using pipeline and retime techniques. Simulation results show that it has 5. 7 ns propagation delay and 2. 65 mW power consumption. The figure of merit for energy consumption is 15. 2 PJ. The proposed multiplier has been designed using 0. 18 μ m TSMC process at 1. 8 V supply and simulated using Cadence tools. The layout of the multiplier occupies 52414 μ m 2.

Nowadays, the use of hardware/software codesign has grown dramatically in the design of embedded systems since it can improve the processing power, system efficiency, and the total cost of production. In this method, some parts of the system are implemented in hardware and the other parts are implemented in software in order to satisfy the system constraints, including power consumption, area and processing time. This paper proposes a Parallel Architecture for motion estimation in HEVC encoder. In the proposed method, the motion estimation part of the encoder, which has a high computational complexity, is implemented in hardware, and the computational complexity of this part is improved using Parallel processing. The hardware implementation of motion estimation part is much less complex than the adopted HM reference software, making it more suitable for embedded systems. Experimental results show a significant improvement over software implementation.

This paper presents two efficient implementations of fast and pipelined Bit-Parallel polynomial basis multipliers over GF (2m) by irreducible pentanomials and trinomials. The Architecture of the first multiplier is based on a Parallel and independent computation of powers of the polynomial variable. The second structure only even powers of the polynomial variable are used. The Parallel computation provides regular and low-cost structure with low critical path delay. In addition, the pipelining technique is applied to the proposed structures to shorten the critical path and to perform the computation in two clock cycles. The implementations of the proposed methods over the binary extension fields GF (2163) and GF (2233) have been successfully verified and synthesized using Xilinx ISE 11 by Virtex-4, XC4VLX200 FPGA.

The forward position kinematics (FPK) of a Parallel manipulator with new Architecture supposed to be used as a moving mechanism in a flight simulator project is discussed in this paper. The closed form solution for the FPK problem of the manipulator is first determined. It has, then, been shown that there are at most 24 solutions for FPK problem. This result has been verified by using other techniques such as geometric approach and a numerical method known as polynomial continuation. Numerical examples are performed to display all possible solutions available for the devised manipulator.

This paper presents a new Architecture design for planar Parallel manipulators, which helps greatly to increase their maneuverability and enlarging their workspace. In many cases it is very difficult to express interlace of links as constraint and it is an obstacle, which doesn"t let the computations for kinematics, or workspace is the same as in practical case. This new architectural design makes this wish comes true for computation and practical cases. To show how it works, a 3-DOF planar Parallel manipulator is selected. In the mechanism, the prismatic actuators are fixed to the base which leads to a reduction of the moving links inertia, hence makes it attractive, particularly when high speeds are required and electric actuation is considered. First, the mechanism is introduced; then a new design is introduced based on the geometry of the manipulator to increase flexibility and accessibility. Finally a workspace analysis is performed. Optimization of workspace is considered with 3 different methods: Monte Carlo, Exact Method (introduced for the first time) and Global Condition Index. Then the results are compared.